There is a persistent goal in the semiconductor industry to reduce the size of structural elements within an integrated circuit chip. In static memory cells, for example, resistors rather than transistors are frequently used as load elements in order to avoid requiring that more circuit elements be placed in the semiconductive substrate. The resistor may be located above other active elements in the substrate and therefore the static memory cell can occupy less total space. However, resistors themselves may occupy more area than desired because a typical resistor requires a contact area to connect other elements to the resistor, and this contact area also occupies space that could be used for other elements. It is beneficial to reduce the space occupied by the contact area.
Also, since successive layers in an integrated circuit structure are patterned using separate masks, space must be allocated for misalignment of one mask with respect to the next. A process which reduces the space needed for misalignment or for forming the contacts reduces the total space which must be used for a circuit element. This in turn increases the speed with which an integrated circuit can operate and the number of elements which can be located in an integrated circuit of a given size.
FIGS. 1.1a through 1.7b show top and side views respectively of steps and the resulting structure of a prior art resistor 13r. FIGS 1.1b through 1.7b are cross-sectional side views of FIGS. 1.1a through 1.7a respectively, taken along the line A--A. The same reference numerals indicate the same elements in successive figures. As shown in FIG. 1.1b, onto a substrate 11 is formed structure 12, which may comprise an oxide layer, an oxide layer covered by a nitride layer, or may comprise a more complex structure including more than one layer of oxide, polycrystalline silicon and other materials. The top portion of layer 12, however, is an insulator. To form a resistor, onto layer 12 is applied a highly resistive material, for example, undoped or lightly doped polycrystalline silicon layer 13, as shown in FIGS. 1.1a and 1.1b, typically 1000-5000.ANG. thick.
As shown in FIGS. 1.2a and 1.2b, layer 13 is patterned to form a structure 13p which will comprise both a resistor and its conductive contact regions. As shown in FIGS. 1.3a and 1.3b, a protective layer 14 which may be of insulating material, including oxide or oxide and nitride, or, alternatively photoresist, is formed on the surface of the structure, contacting resistive structure 13p and exposed portions of layer 12. Layer 14 is patterned, as shown in FIGS. 1.4a and 1.4b, to form mask 14p, exposing resistive structure 13p except at a location beneath part of mask 14p which will remain highly resistive. As shown in FIG. 1.5b, an impurity doping is performed, for example by diffusion or ion implantation, producing doped regions 15a and 15b, and leaving a resistor 13r beneath mask 14p. Because the doped impurity diffuses upon subsequent heating, the highly doped regions 15a and 15b extend beneath mask 14p. In order to retain a sufficiently high resistance of resistor 13r (FIG. 1.5b) the final length of resistor 13r between the two conductive regions 15a and 15b is normally about 1.0 to 1.2 microns. Because the lateral diffusion extends approximately 1.0 to 1.25 microns beneath each edge of mask 14p, the length of protective region 14p must typically be 3.0 to 3.5 microns.
Space allocation for protective region 14p is less if the materials used do not require an implant with resulting lateral diffusion. In such a case, protective region 14p may be as short as 1.0 to 1.2 microns
As shown in FIGS. 1.6a and 1.6b, an oxide layer 16 has been applied and patterned to open vias 16a and 16b, exposing contact points in regions 15a and 15b. Finally, as shown in FIGS. 1.7a and 1.7b, conductive layer 17, often aluminum, but also feasibly polycrystalline silicon or a refractory silicide such as PtSi, WSi.sub.2, TiSi, TaSi.sub.2, or MoSi.sub.2, is applied to the surface of the structure and patterned to leave conductive lines 17a and 17b.
In addition to the 1.0 to 1.2 micron spacing for the resistor mask, an additional allowance of some 0.5 micron at each end must be allowed for misalignment of contact openings 16a and 16b with respect to resistor 13r.
Allowing a minimum size of 1.2 microns for each of the contact openings 16a and 16b, 1.0 to 1.2 microns for the resistor 13r (necessary to assure a desired resistance of several hundred gigaohms to several teraohms), and 0.5 micron at each end for misalignment, the total length of the prior art structure of FIGS. 1.1a through 1.7b remains about 4.4-4.6 microns.